Acceleration of the programming of a memory module with the aid of a boundary scan (bscan) register

ABSTRACT

In order to program a memory module, some of its inputs are stimulated via internal memory locations of a so-called boundary scan (BSCAN) register that is provided in the form of an IC or ASIC. In order to activate or deactivate a write operation, the control signal input of the memory module, said control signal input being responsible for generating a WRITE_ENABLE signal, is controlled exclusively. The switching over of the WRITE_ENABLE signal from “LOW” to “HIGH” potential and vice versa thus ensues according to two JTAG instructions of an instruction sequence that provides for the generation of a LOW or HIGH level at the setting signal input or resetting signal input of an update flip-flop of the memory location responsible for generating the WRITE_ENABLE signal. By appropriately modifying the control unit and the BSCAN cell, which stimulates the WRITE_ENABLE signal at the WR input of the memory module, the programming can be accelerated without having to expand the interface between the control unit and the BSCAN register to the board and equipment level. In another embodiment of the invention, a control unit automatically switches over the WRITE_ENABLE signal from “LOW” to “HIGH” potential or from HIGH to LOW potential at an appropriate or rather programmable point in time by setting or resetting the update flip-flop of the memory location responsible for generating the WRITE_ENABLE signal.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is the U.S. National Stage of International ApplicationNo. PCT/DE2003/002932, filed Sep. 3, 2003 and claims the benefitthereof. The International Application claims the benefits of Germanapplication No. 10244977.5 filed Sep. 26, 2002, both applications areincorporated by reference herein in their entirety.

FIELD OF THE INVENTION

The invention relates to the acceleration of the programming of a memorymodule with the aid of a Boundary Scan (BSCAN) register.

BACKGROUND OF THE INVENTION

Boundary Scan (BSCAN) is a standardized method of board testing of theJoint Test Access Group (JAG), a consortium founded in 1988 comprisingover 200 companies from the semiconductor, testing and systemintegration fields, and in 1990 the method was formally approved asindustry standard IEEE I'D for Test Access Port (TAP) and Boundary Scan(BSCAN) architectures. All connection tests at board level in theproduction of complex Printed Circuit Boards (PCBs) are based on thisspecification. If the object under test has its own microprocessor aswell as flash-based program memory, a built-In self-test can for examplebe implemented by loading a flash memory via Boundary Scan with the aidof a self-test program. Test results stored in the memory can again beread out using Boundary Scan once the test has ended.

IEEE 1149.1 is today increasingly replacing In-Circuit Test (ICT)methods since the complexity of the integrated semiconductor circuits(ASICs and FPGAs) to be tested is increasing and as a result thepossibility of accessing these components for test purposes, byproviding additional test pads on the test object, is becoming ever moredifficult. Thus, over the last decades, an exponential increase of thenumber of connection pins with diameters becoming increasingly smallerhas been seen. This trend was accelerated even further by theintroduction of the Ball Gate Array (BGA) technology, which brought withit the relocation of the connecting pins to the underside of the module.The solution lay in integrating conventional tests on microchips, suchas interruption or short circuit tests, into the chips themselves andplanning in a path referred to as the “boundary” for scanning thedigital information. Flexible platforms in accordance with thePeripheral Component Interconnect (PCI) or PCI Extensions forInstrumentation (PXI) Standard currently allows the detection of BSCANcontrollers and BSCAN software as well as its integration into therelevant PCI or PXI platform. This enables complex solutions to bedeveloped combing conventional function tests and BSCAN-based tests intoone universal test platform.

To execute Boundary Scan tests two conditions must be met: At least afew of the integrated circuits (ICs) on the board must comply with theBoundary Scan specification. During testing a BSCAN register is thenmade to perform the desired test with the aid of test vectors. Inaddition the product developer must make available a scan path betweenthe individual ICs which leads from a Test Access Port (TAP) through theICs back again to the TAP where the data is finally scanned. For testingof electrical connections Boundary Scan tests represent an excellentalternative to In-Circuit Tests (ICTs). The costs for performing thefunction testing are low, and because of the increasing integration andminiaturization of terminals, it can be assumed that there will be acontinuing trend towards Boundary Scan.

Whereas the Boundary Scan method according to IEEE 1149.1 has previouslyprimarily been used as an innovative technology for function checking ofintegrated circuits or for verification and simulation of hardwaremalfunctions, recent developments have shown that there are furtherpossible applications for this principle. As well as its use for testpurposes, Boundary Scan is also very effectively deployed forin-system-programming of flash memories and also Programmable LogicDevice (PLD) chips, for example Field Programmable Gate Arrays (FPGAs)with up to 10,000 logic gates per array, or Programmable Logic Arrays(PLAs). In this case the individual control and address inputs of aflash memory are stimulated via the chained BSCAN cells of a BSCANregister assigned to these inputs such that a read or write operation isoptionally initiated. As can be seen from the basic functional diagramshown in FIG. 1, the data here can be output or recorded by thecorresponding BSCAN cells.

FIG. 3 shows information about the steps required which have to beinitiated via the TAP Controller for a write or programming operation.In a first step the address, data and a Module Select (CS) signal areoutput. Then the WRITE signal is activated in a second step, withnothing changing in the other signals. Finally, in a third step theWRITE signal is deactivated without changing the other signals.

The problem is that programming is made very time-consuming by thismethod since three cycles of the entire BSCAN register are required forone write operation.

Conventional methods in accordance with the prior art resolve thisproblem either by shortening the BSCAN chain or by direct control of theWRITE input:

-   -   a) Since the programming time depends on the length of the BSCAN        chain, the programming can be accelerated in the first case by        reducing the chain by the BSCAN cell necessary for flash        programming and activating with a separate instruction (SHORTEX)        instead of the usual instruction (EXTEST).    -   b) In the last case the flash memory can be stimulated directly        with the aid of an additional signal which is output via the TAP        Controller defined in the IEEE 1149.1 Standard. This requires        the test or programming equipment to support the control of an        additional signal and an additional pin to be provided on the        module for this interface embodied as a plug-in connection.

SUMMARY OF THE INVENTION

Using the above-mentioned prior art as its starting point, the object ofthe present invention is to provide a method for programming a memorymodule by individual stimulation of its control signal and/or addressinputs via memory cells of a BSCAN register for the purposes ofgenerating a WRITE_ENABLE signal to activate or deactivate a writeoperation, with the aid of which the time needed for programming of thememory module can be decisively reduced.

In accordance with the invention this object is achieved by the featuresof the independent patent claims. Advantageous exemplary embodimentswhich further develop the idea behind the invention are defined in thedependent patent claims.

within the framework of the inventive solution—in accordance with theobject of the invention defined in the previous section—a method andalso a control unit for programming a memory module by stimulatingindividually its control signals, data and/or address inputs viainternal memory cells of a Boundary Scan (BSCAN) register is provided,which is realized as an application-specific integrated circuit (ASIC).To activate or deactivate a write operation in this case exclusively thecontrol input of the memory module responsible for the generation of aWRITE ENABLE signal is controlled.

Through a modification of the TAP controller as well as the BSCAN cellwhich stimulates the WRITE_ENABLE signal at the input of the flashmemory, the flash-programming can be significantly accelerated, withoutthe TAP interface having to be expanded at board and equipment level.

BRIEF DESCRIPTION OF THE DRAWINGS

Further characteristics, features, advantages and applications of theunderlying invention are produced by the subordinate dependent patentclaims as well as by the following description of two exemplaryembodiments of the invention, which are depicted in FIGS. 2, 4 and 5.The Figures show

FIG. 1 the basic diagram of a circuit arrangement for executing aBoundary Scan (BSCAN) method for the purposes of programming aprogrammable flash EPROM according to the prior art,

FIG. 2 an expanded basic diagram of the circuit arrangement forexecuting a BSCAN method for the purposes of programming a programmableflash EPROM in accordance with the prior art with the aid of a TestAccess Port (TAP) Controller,

FIG. 3 the instruction sequence of a FLASH WRITE operation forprogramming a programmable flash EPROM with the aid of a BSCAN registerwith no time saving in accordance with the prior art,

FIG. 4 a first variant of the instruction sequence of a FLASH WRITEoperation for programming a programmable flash EPROM with the aid of aBSCAN register with time saving by means of access via two specialinstructions in accordance with the underlying invention and

FIG. 5 a second variant of the instruction sequence of a FLASH WRITEoperation for programming a programmable flash-EPROM with the aid of aBSCAN register with time saving through access via fixed (if nec.programmable) timing of the TAP controller in accordance with theunderlying invention.

DETAILED DESCRIPTION OF THE INVENTION

The idea behind the inventive solution will be explained in greaterdetail below with reference to the exemplary embodiments shown in FIGS.2, 4 and 5. The meaning of the symbols provided with reference numbersin FIGS. 1 to 4 can be found in the enclosed list of reference numbers.

Within the framework of the present invention there is provision for amodification of the TAP Controller 106 and the BSCAN cell 103, whichstimulates the WRITE_ENABLE signal 301 d of the flash memory 104, whichenables the flash programming to be significantly accelerated withoutthe interface between TAP Controller 106 and BSCAN register 102 beingneeded to be expanded at board and equipment level. Instead themodification takes place in the BSCAN register 102. There are twooptions for doing this, which will be described in greater detail below.

(a) Generation of the WRITE Pulse Using Two Instructions

So that the complete BSCAN register 102 does not have to be loaded againfor each write operation, to bring the BSCAN cell 103 which stimulatesthe WRITE_ENABLE signal 301 d of the flash memory 104 to the desiredpotential, the BSCAN-cell 103 concerned is controlled using two specificJTAG instructions 306 and 308. The instruction “WR_L” ensures a “LOW”potential, the instruction “WR_H” a “HIGH” potential at the relevantBSCAN cell 103. An expanded basic diagram of the circuit arrangement forexecuting a BSCAN method in accordance with this exemplary embodiment ofthe present invention is shown in FIG. 2.

In the TAP Controller 106 a SET_WR or CLEAR_WR respectively is generatedfrom these two instructions 306 or 308 which either sets or resets theupdate flip-flop 108 of the BSCAN cell 103 responsible for thegeneration of the WRITE_ENABLE signal 301 d. Both instructions aretypically encoded with 4 or 8 bits, so that compared to the conventionalsolution in accordance with the prior art, in which to initiate a writeoperation the complete BSCAN register 102 must be reloaded in each case,a clear speed benefit is produced. The BSCAN register 102 stillcomprises around 60 bits, even with its shorter length.

FIG. 4 shows a first variant for the instruction sequence 400 of a FLASHWRITE operation for programming a programmable flash EPROM via a BSCANregister with time saving through access via two specific instructions.After the address, data and the Module Select (CS) have been output(appr. 60 bits) only three further instructions—“WR_L”, “WR_H” and“SHORTEX”—each with 4 bits are necessary. If the clock pulsesresponsible for the state transitions of the WRITE_ENABLE signal 301 dare not taken into account, a relationship of$\frac{T_{P,{ges}}^{{{Erf}.},{AB1}}}{T_{P,{ges}}^{Sdt}} = {\frac{L_{I,{ges}}^{{{Erf}.},{AB1}}}{L_{I,{ges}}^{Sdt}} = {\frac{{1.60\quad{Bit}} + {3.4\quad{Bit}}}{3.60\quad{Bit}} \approx {40\quad\%}}}$is produced, where

-   -   L_(I,ges) ^(Sdt) [bits] gives the total length of the        instruction sequence for use of conventional BSCAN methods        according to the prior art,    -   L_(I,ges) ^(Erf.,AB1) [bits] gives the total length of the        instruction sequence for using the first exemplary embodiment of        the invention described in section (a),    -   T_(P,ges) ^(Sdt) [ns] gives the total duration of a FLASH WRITE        cycle when using conventional BSCAN methods according to the        prior art and    -   T_(P,ges) ^(Erf.,AB1) [ns] gives the total duration of a FLASH        WRITE when using the first exemplary embodiment of the invention        described in section (a).

This means that with this first exemplary embodiment of the method inaccordance with the invention compared to the programming method shownin FIG. 3, a reduction in the programming time of 60% can be achieved.

A further benefit which is produced by this solution lies in the factthat the “HIGH” or “LOW” level values of the WRITEENABLE signals 301 dcan be generated in any given timing sequence, with this sequence beingable to be controlled by the instructions 306 and 308.

(b) Automatic Generation of the WRITE Pulse

So that the complete BSCAN register 102 does not always have to bereloaded in order to bring the BSCAN cell 103, which stimulates theWRITE_ENABLE signal 301 d of the flash memory 104 to the desiredpotential, the BSCAN cell 103 involved will be controlled automaticallyduring the application of the address, data and the Module Select (CS)signal at the BSCAN register 102 by the TAP Controller 106 so that aWRITE pulse is generated at a suitable point in time.

FIG. 5 shows a second variant for the instruction sequence 500 of aFLASH WRITE operation for programming a programmable Flash EPROM 104 viaBSCAN register 102 with time saving through access via fixed timing ofthe TAP Controller 106.

This timing of the TAP Controller can if necessary be programmed viafurther registers which can loaded via further instructions.

TAP Controller 106 automatically generates a SET_WR or CLEAR_WR pulse ineach case which either sets or resets the update flip-flop 108 of BSCANcell 103. Since the automatic may not occur for each BSCAN EXTEST orSHORTEX instruction, either a separate command (EXFLASH) is to beintroduced or the TAP Controller 106 is notified before the EXTESTinstruction by an additional instruction (“WR_ON”) that a WRITE impulseis to be generated automatically. This function can be reset inaccordance with the invention with the aid of a further instruction(“WR_OFF”).

The duration of the WRITE pulse can also be set by means of anadditional data register programmed via the TAP interface. FIG. 5 showsthe timing sequence. The diagram clearly shows that only one JTAGinstruction (EXFLASH) is necessary. If the clock pulses responsible forthe state transitions of the WRITE_ENABLE signal 301 d are not takeninto account, a relationship of$\frac{T_{P,{ges}}^{{{Erf}.},{AB2}}}{T_{P,{ges}}^{Sdt}} = {\frac{L_{I,{ges}}^{{{Erf}.},{AB2}}}{L_{I,{ges}}^{Sdt}} = {\frac{1.60\quad{Bit}}{3.60\quad{Bit}} \approx {33.3\quad\%}}}$is produced, where

-   -   T_(P,ges) ^(Sdt) [bits] gives the total length of the        instruction sequence for use of conventional BSCAN methods        according to the prior art,    -   L_(I,ges) ^(Erf.,AB2) [bits] gives the total length of the        instruction sequence for use of the second exemplary embodiment        of the invention described in ring section (b),    -   T_(P,ges) ^(Sdt) [ns] gives the overall duration of a FLASH        WRITE cycle with use of the conventional BSCAN according to the        prior art and    -   T_(P,ges) ^(Erf.,AB2) [ns] gives the total duration of a FLASH        WRITE when using the second exemplary embodiment of the        invention described in section (b).

This means that with this second exemplary embodiment of the method inaccordance with the invention, compared to the programming method inaccordance with the prior art shown in FIG. 3 a reduction in theprogramming time by about 66.7% can be achieved, since only the loading(SHIFT-DR) of a combined address and data block. of 60 bits in size isnecessary.

The underlying invention is based on a method and a control unit forprogramming a memory module by stimulating its individual controlsignals, data and/or address inputs via internal memory cells of what isknown as a Boundary Scan (BSCAN) register which is realized as anintegrated circuit (IC or ASIC). To activate or deactivate a writeoperation in this case exclusively the control input responsible for thegeneration of a WRITE_ENABLE signal of the memory module is controlled.

The invention further comprises a control unit for programming a memorymodule by stimulating individual inputs of the memory module via atleast one memory cell of a BSCAN register for generating a WRITE_ENABLEsignal for the purposes of activating or deactivating a write operation,the control unit adapted for automatically switching the WRITE_ENABLEsignal from “LOW” to “HIGH” potential or from “HIGH” to “LOW” potentialby a control unit, wherein an update flip-flop of the memory cellresponsible for the generation of the WRITE_ENABLE signal is set orreset.

The invention further comprises a memory cell of a BSCAN register (102),which is used when programming a memory module (104) for stimulation ofindividual inputs (CS, OE, WR, ADDR, DATA) of the memory module (104)for the purposes of initiating or ending a write operation, the memorycell adapted for exclusively activating a control signal input of thememory module responsible for activating or deactivating a writeoperation, wherein a switch-over of a WRITE ENABLE signal fed to thecontrol signal input by the memory cell from “LOW” to “HIGH” potentialor from “HIGH” to “LOW” potential is controlled using an instructionsequence fed to inputs of an update flip-flop of the memory cell, theupdate flip-flop generating the WRITE ENABLE signal having a “LOW” levelor a “HIGH” level based on the instruction sequence.

The invention further comprises a memory cell of a BSCAN register (102),which is used when programming a memory module (104) for stimulation ofindividual inputs (CS, OE, WR, ADDR, DATA) of the memory module (104)for the purposes of initiating or ending a write operation, the memorycell adapted for automatically switching a WRITE_ENABLE signal from“LOW” to “HIGH” potential or from “HIGH” to “LOW” potential by a controlunit, wherein an update flip-flop of the memory cell responsible for thegeneration of the WRITE_ENABLE signal is set or reset.

The invention further comprises a BSCAN register, consisting of a numberof memory cells (103) for control of a programmable memory module (104),which is used for stimulation of individual inputs (CS, OE, WR, ADDR,DATA) of the memory module (104) for the purposes of initiating orending a write operation, the BSCAN register adapted for performing amethod for programming a memory module by stimulating individual inputsof the memory module via at least one memory cell of the BSCAN registerby exclusively activating a control signal input of the memory moduleresponsible for activating or deactivating a write operation, wherein aswitch-over of a WRITE ENABLE signal fed to the control signal input bythe memory cell from “LOW” to “HIGH” potential or from “HIGH” to “LOW”potential is controlled using an instruction sequence fed to inputs ofan update flip-flop of the memory cell, the update flip-flop generatingthe WRITE ENABLE signal having a “LOW” level or a “HIGH” level based onthe instruction sequence.

The invention further comprises a BSCAN register, consisting of a numberof memory cells (103) for control of a programmable memory module (104),which is used for stimulation of individual inputs (CS, OE, WR, ADDR,DATA) of the memory module (104) for the purposes of initiating orending a write operation, the BSCAN register adapted for performing amethod for programming a memory module by stimulating individual inputsof the memory module via at least one memory cell of the BSCAN registerfor generating a WRITE_ENABLE signal for the purposes of activating ordeactivating a write operation, by automatically switching theWRITE_ENABLE signal from “LOW” to “HIGH” potential or from “HIGH” to“LOW” potential by a control unit, wherein an update flip-flop of thememory cell responsible for the generation of the WRITE_ENABLE signal isset or reset.

1-13. (canceled)
 14. A method for programming a memory module bystimulating individual inputs of the memory module via at least onememory cell of a Boundary Scan Register (BSCAN), the method comprising:exclusively activating such control signal input of the memory moduleresponsible for activating or deactivating a write operation, wherein aswitch-over of a WRITE ENABLE signal fed to the control signal input bythe memory cell from “LOW” to “HIGH” potential or from “HIGH” to “LOW”potential is controlled using an instruction sequence fed to inputs ofan update flip-flop of the memory cell, the update flip-flop generatingthe WRITE ENABLE signal having a “LOW” level or a “HIGH” level based onthe instruction sequence.
 15. The method according to claim 14, whereinthe “LOW” or “HIGH” levels at the inputs of the update flip-flop can begenerated in any given timing sequence.
 16. The method according toclaim 14, wherein the timing sequence of the “LOW” or “HIGH” levels atthe setting signal input or resetting signal input of the updateflip-flop is controlled by the instruction sequence.
 17. The methodaccording to claim 15, wherein the timing sequence of the “LOW” or“HIGH” levels at the setting signal input or resetting signal input ofthe update flip-flop is controlled by the instruction sequence.
 18. Themethod according to claim 14, wherein the signals for theupdate-flip-flop are generated by a control unit based on theinstruction sequence.
 19. The method according to claim 15, wherein thesignals for the update-flip-flop are generated by a control unit as afunction of the instruction sequence.
 20. The method according to claim16, wherein the signals for the update-flip-flop are generated by acontrol unit as a function of the instruction sequence.
 21. A method forprogramming a memory module by stimulating individual inputs of thememory module via at least one memory cell of a BSCAN register forgenerating a WRITE_ENABLE signal for the purposes of activating ordeactivating a write operation, the method comprising: automaticallyswitching the WRITE_ENABLE signal from “LOW” to “HIGH” potential or from“HIGH” to “LOW” potential by a control unit, wherein an update flip-flopof the memory cell responsible for the generation of the WRITE_ENABLEsignal is set or reset.
 22. The method according to claim 21, whereinthe automatic generation of a setting signal for activating the writeoperation can be activated by the control unit using a programmingcommand.
 23. The method according to claim 22, wherein the automaticgeneration of the setting signal can be prevented if specificinstructions are present.
 24. The method according to claim 21, whereina further instruction is used, with which the control unit can benotified that a setting signal for activating the write operation is tobe automatically generated.
 25. The method according to claim 21,wherein a further instruction is used, with which the control unit canbe notified that a reset signal for deactivating the write operation isto be automatically generated.
 26. The method according to claim 24,wherein a further instruction is used, with which the control unit canbe notified that a reset signal for deactivating the write operation isto be automatically generated.
 27. The method according to claim 21,wherein the suitable point in time for automatic switchover of theWRITE_ENABLE signal is programmed by suitable instructions.
 28. Acontrol unit for programming a memory module by stimulating individualinputs of the memory module via at least one memory cell of a BoundaryScan Register (BSCAN), the control unit adapted for exclusivelyactivating a control signal input of the memory module responsible foractivating or deactivating a write operation, wherein a switch-over of aWRITE ENABLE signal fed to the control signal input by the memory cellfrom “LOW” to “HIGH” potential or from “HIGH” to “LOW” potential iscontrolled using an instruction sequence fed to inputs of an updateflip-flop of the memory cell, the update flip-flop generating the WRITEENABLE signal having a “LOW” level or a “HIGH” level based on theinstruction sequence.